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| 74F823 9-Bit D-Type Flip-Flop April 1988 Revised August 1999 74F823 9-Bit D-Type Flip-Flop General Description The 74F823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. Features s 3-STATE outputs s Clock Enable and Clear Ordering Code: Order Number 74F823SC 74F823SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Logic Symbols Connection Diagram IEEE/IEC (c) 1999 Fairchild Semiconductor Corporation DS009596 www.fairchildsemi.com 74F823 Unit Loading/Fan Out Pin Names D0-D8 OE CLR CP EN O0-O8 Description Data Inputs Output Enable Input Clear Clock Input Clock Enable 3-STATE Outputs U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 150/40 (33.3) Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-1.2 mA 20 A/-0.6 mA -3 mA/24 mA (20 mA) Functional Description The 74F823 device consists of nine D-type edge-triggered flip-flops. It has 3-STATE true outputs and is organized in broadside pinning. The buffered Clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flipflops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOWto-HIGH CP transition. With the OE LOW the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. In addition to the Clock and Output Enable pins, the 74F823 has Clear (CLR) and Clock Enable (EN) pins. When the CLR is LOW and the OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flipflops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH, the outputs do not change state regardless of the data or clock inputs transitions. This device is ideal for parity bus interfacing in high performance systems. Function Table Inputs OE CLR EN CP D H H H L H L H H L L L L H H H H L L H H H H H H L L H H X X L L L L L L H L X X X X X X X X X H H L H X X Internal Output Function Q NC NC NC NC H H H L H L NC NC O Z Z Z NC Z L Z Z L H NC NC Hold Hold Hold Hold Clear Clear Load Load Data Available Data Available No Change in Data No Change in Data X H L L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F823 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Buss Drainage Test Power Supply Current 75 -60 4.75 3.75 -0.6 -1.2 50 -50 -150 500 100 10% VCC 2.5 2.4 2.7 2.7 0.5 5.0 7.0 50 V A A A V A mA mA A A mA A mA Min Max Max Max 0.0 0.0 Max Max Max Max Max 0.0V Max V Min Min 2.0 0.8 -1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -3 mA IOH = -1 mA IOH = -3 mA IOL = 24 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (OE, CLR, EN) VIN = 0.5V (CP) VOUT = 2.7V VOUT = 0.5V VOUT = 0V VOUT = 5.25V VO = HIGH Z 3 www.fairchildsemi.com 74F823 AC Electrical Characteristics TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CLR to On Output Enable Time OE to On Output Disable Time OE to On 100 2.0 2.0 4.0 2.0 2.0 1.5 1.5 VCC = +5.0V CL = 50 pF Typ 160 5.6 5.2 7.1 5.8 5.5 2.9 2.7 9.5 9.5 12.0 10.5 10.5 7.0 7.0 Max TA = -55V to +125C VCC = +5.0V CL = 50 pF Min 60 2.0 2.0 4.0 2.0 2.0 1.0 1.0 10.5 10.5 13.0 13.0 13.0 7.5 7.5 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 70 2.0 2.0 4.0 2.0 2.0 1.5 1.5 10.5 10.5 13.0 11.5 11.5 7.5 7.5 ns Max MHz ns ns Units AC Operating Requirements TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(L) tREC Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Setup Time, HIGH or LOW EN to CP Hold Time, HIGH or LOW EN to CP CP Pulse Width HIGH or LOW CLR Pulse Width, LOW CLR Recovery Time 2.5 2.5 2.5 2.5 4.5 2.5 2.0 0 5.0 5.0 5.0 5.0 Max TA = -55V to +125C VCC = +5.0V Min 4.0 4.0 2.5 2.5 5.0 3.0 3.0 1.0 6.0 6.0 5.0 5.0 Max TA = 0C to +70C VCC = +5.0V Min 3.0 3.0 2.5 2.5 5.0 3.0 2.0 0 6.0 6.0 5.0 5.0 ns ns ns ns ns Max Units www.fairchildsemi.com 4 74F823 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74F823 9-Bit D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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